The present invention relates to a semiconductor device, particularly, to a semiconductor package having a structure which is adequate for decreasing the electrical resistance of the semiconductor package without a Si chip.
An example of a conventional transistor package is disclosed in JP-A-8-64634 (1994). A semiconductor chip, whereon electronic circuits are formed, is bonded to a die pad for heat release at a rear plane electrode side by welding. A bump is formed on an Al electrode at a circuit formed plane side of the chip, and an inner lead is connected electrically and mechanically thereon. An inner lead is also connected to the die pad, and the chip, the die pad, and a part of the lead is sealed with resin so as to cover them. In a case when the bump is solder, the lead side is plated with tin (Sn), gold (Au), or solder, and the like, and bonded with the bump by melting the solder of the bump. In a case when the bump is gold, the lead is plated with tin, and bonded with the bump by an Auxe2x80x94Sn eutectic reaction. The inner lead is composed of three lines provided for a source electrode, a drain electrode, and a gate electrode, respectively. The lead for the source electrode is manufactured in a comb teeth shape. A through opening to the resin is formed on the head.JP-A-5-121615 (1993) discloses a surface mounting type semiconductor package having a wireless structure as another conventional example. Three external connection terminals are connected to electrode terminals of the semiconductor chip. Two electrodes on an upper surface of the chip are connected to the external connection terminals by thermocompression bonding of Au balls. Mounting on a circuit substrate is performed by soldering the tip region of the lead terminals, which protrude forward and backward from the chip mounting portion, to the terminals of the substrate.
In accordance with a conventional standard surface mounting type semiconductor package, the semiconductor chip is bonded to the die pad of the lead for the drain by soldering, and the source electrode and the gate electrode of the semiconductor chip are connected to the leads for the source and the gate of the external connection terminals by Al wire bonding. The chip, each respective lead, and a part of the die pad are molded with resin. The die pad is exposed at the bottom of the resin body so as to allow the structure of the resin body to be connected to the circuit substrate, and its size is set to be larger than the size of the resin mold.
In accordance with the conventional chip die pad bonding structure of a semiconductor chip, a bonding structure using a resin with conductive particles, wherein Pb rich solder having a low yield strength or Ag particles are mixed, has been adopted in order to prevent the chip from generating a high stress when the chip is fixed to a member made of a Cu base alloy.
The electrical resistance of the semiconductor package without a Si chip in the surface mounting type plastic package of a conventional vertical semiconductor element has been from several tens mxcexa9 to ten and several mxcexa9 with a wire bonding structure. In accordance with advancement of semiconductor technology, the on-resistance of the element has been decreasing year by year, and at present, a device of several tens to several mxcexa9/cm2 has been developed. Further decrease of the resistance can be expected in future. In that case, a decrease of the electrical resistance of the semiconductor package without a Si chip is indispensable for improving the performance of the semiconductor package, because the electrical resistance of a semiconductor package without a Si chip becomes larger than the device resistance. A prior technique regarding the on-resistance of the semiconductor package is disclosed in JP-A-8-64634. The prior proposed technique relates to an insert mounting type package. The insert mounting type package is not restricted in size, and a thick and large size die pad can be used, because the bonding between the substrate and the lead is strong structurally. Therefore, a decrease of the electrical resistance of the semiconductor package without a Si chip is relatively easy. However, the surface mounting type package has a property that the fatigue strength of the bonding portion is weaker than that of the insert mounting type package, because it has a structure in which the tip of the leads protruding from both sides of the resin body are bonded to the terminal of the substrate by soldering two planes of small area to each other. Therefore, it is necessary to absorb the thermal strain between the package and the substrate resulting from heat generation of the chip which causes deformation of the flexible leads. Accordingly, it is necessary to make the shape of the leads thin and slender. In this case, a decrease of the electrical resistance of the semiconductor package without a Si chip is difficult, because the electrical resistance of the lead itself is large.
In the case of a surface mounting type package, the above problem can be solved by adopting a structure wherein the die pad mounting the chip is soldered directly to the circuit substrate. However, if a position where the lead, to be connected to the electrode at an upper surface of the chip, protrudes from the resin body differs in height from the position where the die pad protrudes, the contacting planes of the upper and lower metal molds for molding the resin form a three dimensional structure, such that a problem is created in that the manufacture of the metal molds becomes difficult. The above problem becomes significant when the lead frame is a matrix frame (arranged in X and Y directions) and the objective is to manufacture a large number of the packages, simultaneously. The problem can be solved by making the size of the die pad to be contained in the resin body small, but if so, a pressing portion to press the die pad onto the bottom surface of the metal mold must be provided in the metal mold, in order to expose the die pad at the lower plane of the resin body. If the size of the die pad is sufficiently large, it is possible to press the die pad onto the bottom surface of the metal mold. However, if the size of the die pad is the same as the size of the chip, the pressing portion can not be found on the die pad, and a problem is created in that the die pad is molded while being exposed at the bottom of the resin body. Therefore, in case of a small size semiconductor package, wherein the size of the die pad is the same as the size of the chip, it is difficult to assembly the structure in such a manner that the die pad concurrently operating as the external connection terminals of the rear electrode is contained in the resin body.
On the other hand, conventionally, a soldering connection or an adhering structure with a resin using conductive particles has been adopted for the connection of the rear plane of the chip with the external connection terminals, such as a die pad, and others. The soldering connection is a superior connection with regard electrical resistance, thermal resistance, and heat resistance reliability. However, currently, in view of environmental problems, no use of Pb is employed, and the conventional soldering material containing Pb must be replaced with a new bonding material containing no Pb. There are various soldering materials containing no Pb having a solidus line temperature below 250xc2x0 C., but actually, there is no adequate soldering material containing no Pb having a solidus line temperature higher than 270xc2x0 C., which is durable against severe mounting on the substrate of the package. The only exception is Auxe2x80x94Si solder having a solidus line temperature of 370xc2x0 C. However, Auxe2x80x94Si solder can not be adopted as the soldering material for the electrode at the rear plane of the chip, for two reasons, such as high cost and generation of cracks in the chip during the cooling step after soldering when the size of the chip is large, because of the high yield strength. Therefore, a problem exists in that there is no soldering material containing no Pb to replace the soldering material containing Pb. On the other hand, adhesion with a resin with conductive particles is durable thermally in a short time against the necessary temperature for the mounting ,.i.e. 270xc2x0 C., but is weak in mechanical strength, because the adhesion strength is maintained by the resin. Even though tightness of the adhesion is reinforced with a shrinking force by curing the molding resin, a package having a large area or a package used in a high temperature has a problem in that the electric resistance and thermal resistance at the bonding portion are increased in accordance with deterioration of the resin, which is caused by a change with elapsing time or temperature cycles. In particular, because the one plane molding structure, wherein the die pad (external connection terminals) is exposed to the surface of the resin body, is a structure which can not receive sufficient pressing force from the molding resin at the rear plane of the chip, a problem is raised in that the long term reliability of the resin using conductive particles for adhesion is further decreased.
The present invention has been achieved in consideration of the above problems, and has the object of providing a semiconductor device comprising a package structure which can decrease the electrical resistance of the semiconductor package without a Si chip.
The semiconductor device in accordance with the present invention is provided with a semiconductor element, which comprises a semiconductor substrate, a first electrode provided at the front plane of the semiconductor substrate, and a second electrode provided at the rear plane of the semiconductor substrate. A first metallic member is connected to the first electrode of the semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is connected to the second electrode of the semiconductor element via a second metallic body containing a second precious metal.
In accordance with the present invention, the electrical resistance of the semiconductor package without a Si chip can be decreased, because the first and second members are connected to the electrodes of the semiconductor element via the metallic bodies containing different precious metals.
In accordance with the above composition, the surface portion of the first metallic member and the surface portion of the second metallic member for connecting to the external wiring are desirably positioned in approximately the same plane. The term xe2x80x9capproximately the same planexe2x80x9d means, for instance, a plane of the wiring substrate or circuit substrate of various electronic devices, whereon electronic members are mounted. Accordingly, the semiconductor device can be mounted onto the wiring substrate or the circuit substrate.
As the first metallic body, there is an protrusion electrode which protrudes from the first electrode or the first metallic member of the semiconductor device. As the protrusion electrode, there are bump electrodes, or ball electrodes made of precious metal, such as gold (Au) or silver (Ag), and others can be used. In order to decrease the electrical resistance of semiconductor package without a Si chip, a plurality of the protrusion electrodes are desirably arranged with approximately the same interval relative to each other on the whole surface of the bonding interface of the first electrode with the first metallic member.
As the second metallic body, a metal layer positioned at the bonding interface of the second electrode with the second metallic member can be used. The metal layer is desirably composed by bonding the respective precious metal layers positioned at bonding front plane sides of the second electrode and the second metallic member, respectively. As the material of the precious metal layer, a precious metal selected from a group consisting of gold (Au), silver (Aq), platinum (Pt), palladium (Pd), and the like, or an alloy containing the above element as a main component can be used. A layer composed of plural kinds of precious metals, or multi-layers of the alloy layer is also usable. Furthermore, any bump electrode or ball electrode made of precious metal, such as gold (Au) or silver (Aq), silver (Ag) particles mixed with resin, a silver (Ag) member in a shape of plate, sheet, or network, and a silver member shaped in plate or sheet having bumps and dips, or cavity portions thereon, may be interposed between the precious metal layer positioned at the second electrode side and the precious metal layer positioned at the second metallic member side. As the desirable other metal layer, an alloy layer containing precious metal as a main component, of which the solidus line temperature is higher than 400xc2x0 C., is usable. As the material of the alloy layer, an alloy of silver (Ag) and tin (Sn) containing silver as the main component can be used.
A precious metal layer may be provided on the bonding surface of the first and second electrodes, and of the first and second metallic members of the semiconductor device. As the material of the above precious metal layer, a precious metal selected from a group consisting of gold (Au), silver (Ag), platinum (Pt), palladium (Pd), and the like, or an alloy containing the above element as a main component can be used. As the material of the first and second electrodes of the semiconductor device, aluminum, or an aluminum alloy such as aluminum-silicon can be used.
The first and second metallic members electrically connect the first and second electrodes of the semiconductor element to external electrodes, the wiring substrate, the circuit substrate, and others. For instance, the first and second metallic members are lead wire, lead electrodes, or die pad terminals, which are a part of the semiconductor package, and others, or a part of these members. In order to decrease the electrical resistance of a semiconductor package without a Si chip, the first metallic member desirably comprises plural portions extending from the portion having the bonding portion with the first electrode, and the plural portions each comprise a surface portion for connecting with external wiring. In accordance with the circuit substrate or wiring substrate connecting to the semiconductor device, each surface portion as described above of the first metallic member is provided with a conductor portion (for instance, copper foil) for electrical connection. The conductor portions are connected electrically on the circuit substrate or the wiring substrate. For instance, a continuous conductor (for instance, copper) pattern can be used as the conductor portion of the printed substrate.
The composition of the semiconductor device in accordance with the present invention as described above can be applied to semiconductor devices, wherein the semiconductor element and the first and second metallic members are coated with an insulating material, such as the resin sealing type or resin molding type semiconductor devices. In these cases, the rear plane of the bonded plane of the first metallic member bonded with the first electrode has desirably an exposed portion for connecting with external wiring. In addition to the above composition, the bonded plane side of the semiconductor element is used as a circuit forming plane (for instance, a plane whereon one of the main current electrodes and a control electrode of the vertical semiconductor switching element are formed), and the first electrode is desirably used as the main current electrode. In accordance with the semiconductor device, wherein the semiconductor element and the first and second metallic members are coated with an insulating material, the rear plane of the bonded plane of the second metallic member bonded with the second electrode may have an exposed portion for connecting with external wiring. As the insulating material, ceramics and other insulators can be used, in addition to various resins.
The various composition described above can be used concurrently. However, some compositions have a function and an advantage to decrease the electrical resistance of the semiconductor package without a Si chip by itself, such as the other semiconductor device of the present invention described hereinafter.
As the other semiconductor device of the present invention, the semiconductor package, which contains a semiconductor element comprising a first electrode and a second electrode on the front plane and the rear plane of the semiconductor substrate, respectively, can be composed in any one of the following ways:
1) A composition, wherein the second electrode and the second metallic member are bonded via a metallic layer; the metallic layer is composed by bonding precious metal layers, one of which is provided on the bonding front plane of the second electrode, and another one of which is provided on the bonding front plane of the second metallic member.
2) A composition, wherein the second electrode and the second metallic member are bonded via an alloy layer; the alloy layer is composed of an alloy containing precious metal as a main component, of which the solidus line temperature is higher than 400xc2x0 C.
3) A composition, wherein the first metallic member comprises plural portions extending from the bonding portion with the first electrode, and each of the plural portions comprises a surface portion for connecting with external wiring.
The composition of 1) or 2), and the composition 3) can be used concurrently.
Each of the semiconductor devices of the present invention described above can be applied to various semiconductor elements, such as a MOS (Metal Oxide Semiconductor) field effect transistor, a MIS (Metal Insulator Semiconductor) field effect transistor, a bipolar transistor, an insulated gate bipolar transistor, a diode, or integrated circuits, and the like. The composition of each of the semiconductor devices of the present invention is preferably applied to the semiconductor element, wherein the first electrode and the second electrode are used as a pair of main current electrodes; and to the vertical type semiconductor element, such as a power MOSFET and power transistor, wherein the first and the second electrodes are used as the main current electrodes, and the main current passes vertically in the semiconductor substrate in a direction from the first electrode at the front plane side to the second electrode at the rear plane side, or in a reverse direction. In this case, the on-resistance or on-voltage between the terminals including the package can be decreased, accompanied with low on-resistance characteristics of the semiconductor element.
In accordance with the semiconductor device of the present invention, the bonding strength of the Au bump/Al electrode bonding portion is improved by changing the Al film between the Au bump/Si substrate to an Auxe2x80x94Al compound in all the thickness direction of more than 80% of the bonding area by heating treatment of the Au bump/Al electrode bonding portion at a high temperature. Furthermore, the temperature cycle life is improved by forming a structure, wherein a compression load is added to the bonding portion by filling a resin between the electrode lead and the chip.